1. Field
The present disclosure generally relates to a phase-interpolator circuit. More specifically, the present disclosure relates to a phase-interpolator circuit in which the output phase is specified using a capacitor divider.
2. Related Art
Phase-interpolator circuits (which are sometimes referred to as ‘phase interpolators’) are important building blocks in modern high-speed clocking systems and serial-link transceivers. Given at least two quadrature clock signals, phase-interpolator circuits can generate output phases over a 360° range. As a consequence, most delay-locked-loops and timing-recovery circuits in high-speed input/output circuits and serial links use phase-interpolator circuits to provide arbitrary clock phases.
Many existing phase-interpolator circuits use active devices to sum the weighted voltages or currents associated with the input clock phases. However, these phase-interpolator circuits have associated nonlinearities, which can limit performance and typically require an increase in the resolution in order to minimize the phase steps in the phase-interpolator circuits, i.e., the differential nonlinearity (DNL). Furthermore, the increased resolution often results in more complicated circuits that occupy more area.
The origins of the nonlinearities in existing phase-interpolator circuits are illustrated in FIGS. 1A-1C. FIG. 1A presents a block diagram illustrating an existing phase-interpolator circuit 100. In this phase-interpolator circuit, a voltage interpolator adds the weighted sum of the input clock-signal voltages, where the weighting of a given clock signal is defined by the strength of an associated clock buffer.
FIG. 1B presents a block diagram illustrating an existing phase-interpolator circuit 130. This phase-interpolator circuit is a variation on phase-interpolator circuit 100 (FIG. 1A). In particular, currents proportional to input clock signals are added together to perform the interpolation (phase-interpolator circuit 130 is sometimes referred to as a type I current interpolator). Note that the interpolation weight is defined by the ratio of currents in the two differential pairs, which can be defined using analog or digital control of the current. Also note that phase-interpolator circuit 130 benefits from the common-mode noise rejection provided by the differential pair.
However, phase-interpolator circuit 130 has a high capacitance, and a nonlinear output impedance. In particular, the weight-change technique is nonlinear because the finite output impedance of the current source causes the current to change nonlinearly even when device dimensions are changed linearly. For example, if the size of the current source is doubled for the same gate voltage, presumably the current will be doubled. But the increase in the current in the differential pair M1 and M2 causes their common-source voltage to drop. This drop is equivalent to a drop in the drain-source voltage of the current source. Therefore, because of the finite output impedance of the current source, the drop in the drain-source voltage results in a current increase that is less than a factor of two.
In addition, nonlinearity associated with interpolation may occur due to capacitive feed-through of a clock signal through the gate-drain capacitance. This feed-through provides an alternative path for the clock signal other than the desired interpolation path. In order to explain this effect, assume that phase-interpolator circuit 130 is programmed to allow clock phase CLKin1 to drive the output, i.e., the contribution associated with clock phase CLKin2 is switched off. Even though phase-interpolator current will be steered to differential pair M1-M2, CLKin2 is fed through to the output by the gate-to-drain capacitance of M3-M4. Moreover, this problem is worse in high-frequency applications where the gate-drain capacitance provides a lower impedance path.
FIG. 1C presents a block diagram illustrating an existing phase-interpolator circuit 160. This phase-interpolator circuit differs from phase-interpolator circuit 130 (FIG. 1B) because phase-interpolator circuit 160 includes additional control switches M5-M8 which isolate the output from the input clock signals (phase-interpolator circuit 160 is sometimes referred to as a type II current interpolator). Note that phase-interpolator circuit 160 alleviates both of the preceding nonlinearities by cascoding transistors M5-M8, and by using a separate differential pair for every phase step. In phase-interpolator circuit 160, changing the interpolation weight now requires changing the weights of all N differential pairs as well (i.e., keeping all N ratios constant, but also driving N differential pairs). However, relative to other existing phase-interpolator circuits, phase-interpolator circuit 160: occupies more area, consumes more power, presents more loading to previous stages, and requires more voltage headroom (i.e., has a smaller output swing). Additionally, splitting up the differential pairs in phase-interpolator circuit 130 (FIG. 1B) into the N separate differential pairs in phase-interpolator-circuit 160 reduces the size of each differential pair, which, in turn, increases the transistor mismatch. This increased transistor mismatch increases the variation in the size of the phase steps in phase-interpolator circuit 160 (FIG. 1C).
Similarly, in phase-interpolator circuit 100 (FIG. 1A), a number of tri-state buffers equal to the number of phase steps are typically used to reduce clock feed-through, and to achieve acceptable linearity performance. However, this configuration also: occupies more layout area, consumes more power, presents more loading to the previous stages, increases the transistor mismatch, and phase-step-size variation.
Hence, what is needed is a phase-interpolator circuit without the above-described problems.